Semiconductor production is becoming less centralized as new foundries are being established across the globe. Some effects of the establishment of new foundries include increasing variations in the fabrication process (i.e., large-scale chip-to-chip variations) and/or increasing local variations in the fabrication process (i.e., small-scale intrachip variations). As an example of a global variation, a buffer in an integrated circuit fabricated by one foundry has a different slew rate than the same type of buffer in the same type of integrated circuit that has been fabricated at a different foundry. As an example of a local variation, two buffers on the same die, having constituent components with ideally identical dimensions, can have different slew rates due to variations in doping.
Capacitive loading of the buffer's output can also vary a buffer's slew rate, as changes in the buffer's output voltage vary the voltage stored by the capacitive portion of the load. Charging and discharging the capacitive portion of the load takes time, and thus the charge/discharge time varies according by the capacitance portion. Also, when the buffer is designed to be coupled to standards-compatible hot-swappable devices or devices having changing capacitive loads, the buffer circuit designer may not know exactly what capacitive load the buffer will encounter, and thus cannot optimize the buffer's slew rate for the unknown capacitive load. In addition to variations in capacitive loading, buffer supply voltage and temperature variations also vary a buffer's slew rate.
As a result of fabrication process, voltage, and temperature (PVT) variations and capacitive loading of the buffer's output, a slew rate of a conventional buffer varies too much for some applications. When the conventional buffer's output slew rate is controlled with a conventional feedback circuit having only a capacitor coupled between the buffer's output and input, the slew rate variations can be mitigated somewhat, but only marginally. In addition, the effectiveness of the conventional feedback circuit varies based on PVT variations, which can drive the output slew rate variation even higher. The slew rate variations in turn change the rail-to-rail rise times and fall times such that the rail-to-rail rise times and fall times vary too much for some applications.
FIGS. 1 and 2 depict conventional output I/O buffer structures 100, 200 with conventional output slew rate control. In FIGS. 1 and 2, a Miller's capacitor (Cfb) 105 is placed between the input node 110 and output node 115 of a basic in/out output buffer 120. As the output slew rate varies across the amount of output capacitive load (Cload) 125, Cfb 105 also starts charging/discharging the input node 110 of the output buffer 120 accordingly, and thus controls the output slew rate of the output buffer 120. With just a simple feedback capacitor Cfb 105, the output buffer 120 is able to achieve some degree of reduction in its output slew rate across different Cload 125, but the slew rate is still subject to full PVT variations, which add a very significant amount of output slew variation to the design.
There are long-felt industry needs for buffer circuits that mitigate the effects of performance variations. Thus, there are needs to address the aforementioned issues by improving upon classic circuit designs and methods.